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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_ll_fifo.html">XLlFifo</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef defines a run-time instance of an <a class="el" href="struct_x_ll_fifo.html" title="This typedef defines a run-time instance of an XLlFifo device. ">XLlFifo</a> device.  <a href="struct_x_ll_fifo.html#details">More...</a><br /></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:gace8f47c03f1818797c152cb27296df7c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#gace8f47c03f1818797c152cb27296df7c">XLlFifo_Reset</a>(InstancePtr)</td></tr>
<tr class="memdesc:gace8f47c03f1818797c152cb27296df7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_Reset resets both the Tx and Rx channels and the local link interface the FIFO specified by <em>InstancePtr</em>.  <a href="group__llfifo__v5__0.html#gace8f47c03f1818797c152cb27296df7c">More...</a><br /></td></tr>
<tr class="separator:gace8f47c03f1818797c152cb27296df7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga095f3e0f8571dc02959852e38237f23e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga095f3e0f8571dc02959852e38237f23e">XLlFifo_Status</a>(InstancePtr)&#160;&#160;&#160;<a class="el" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a>((InstancePtr)-&gt;BaseAddress, <a class="el" href="group__llfifo__v5__0.html#ga90a5fafb06870a7ff8043d3a34bf54cc">XLLF_ISR_OFFSET</a>)</td></tr>
<tr class="memdesc:ga095f3e0f8571dc02959852e38237f23e"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_Status returns a bit mask of the interrupt status register (ISR) for the FIFO specified by <em>InstancePtr</em>.  <a href="group__llfifo__v5__0.html#ga095f3e0f8571dc02959852e38237f23e">More...</a><br /></td></tr>
<tr class="separator:ga095f3e0f8571dc02959852e38237f23e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae65ece5c6c9cce1ccdcf9d404fd8f463"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#gae65ece5c6c9cce1ccdcf9d404fd8f463">XLlFifo_IntEnable</a>(InstancePtr,  Mask)</td></tr>
<tr class="memdesc:gae65ece5c6c9cce1ccdcf9d404fd8f463"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_IntEnable enables the interrupts specified in <em>Mask</em> for the FIFO specified by <em>InstancePtr</em>.  <a href="group__llfifo__v5__0.html#gae65ece5c6c9cce1ccdcf9d404fd8f463">More...</a><br /></td></tr>
<tr class="separator:gae65ece5c6c9cce1ccdcf9d404fd8f463"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabff8f5ef31f09865808da90055e29d42"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#gabff8f5ef31f09865808da90055e29d42">XLlFifo_IntDisable</a>(InstancePtr,  Mask)</td></tr>
<tr class="memdesc:gabff8f5ef31f09865808da90055e29d42"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_IntDisable disables the interrupts specified in <em>Mask</em> for the FIFO specified by <em>InstancePtr</em>.  <a href="group__llfifo__v5__0.html#gabff8f5ef31f09865808da90055e29d42">More...</a><br /></td></tr>
<tr class="separator:gabff8f5ef31f09865808da90055e29d42"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac356d3e8d55aa6e82753400f0bd026a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#gac356d3e8d55aa6e82753400f0bd026a1">XLlFifo_IntPending</a>(InstancePtr)</td></tr>
<tr class="memdesc:gac356d3e8d55aa6e82753400f0bd026a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_IntPending returns a bit mask of the pending interrupts for the FIFO specified by <em>InstancePtr</em>.  <a href="group__llfifo__v5__0.html#gac356d3e8d55aa6e82753400f0bd026a1">More...</a><br /></td></tr>
<tr class="separator:gac356d3e8d55aa6e82753400f0bd026a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac712eea89e9d7fa37d095003c927c61e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#gac712eea89e9d7fa37d095003c927c61e">XLlFifo_IntClear</a>(InstancePtr,  Mask)</td></tr>
<tr class="memdesc:gac712eea89e9d7fa37d095003c927c61e"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_IntClear clears pending interrupts specified in <em>Mask</em> for the FIFO specified by <em>InstancePtr</em>.  <a href="group__llfifo__v5__0.html#gac712eea89e9d7fa37d095003c927c61e">More...</a><br /></td></tr>
<tr class="separator:gac712eea89e9d7fa37d095003c927c61e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3739a78b92f17cead0d831757b3a134"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#gaf3739a78b92f17cead0d831757b3a134">XLlFifo_RxReset</a>(InstancePtr)</td></tr>
<tr class="memdesc:gaf3739a78b92f17cead0d831757b3a134"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_RxReset resets the receive channel of the FIFO specified by <em>InstancePtr</em>.  <a href="group__llfifo__v5__0.html#gaf3739a78b92f17cead0d831757b3a134">More...</a><br /></td></tr>
<tr class="separator:gaf3739a78b92f17cead0d831757b3a134"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaba876eb888126638848fb2f89a9b4436"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#gaba876eb888126638848fb2f89a9b4436">XLlFifo_IsRxEmpty</a>(InstancePtr)</td></tr>
<tr class="memdesc:gaba876eb888126638848fb2f89a9b4436"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_IsRxEmpty returns true if the receive channel of the FIFO, specified by <em>InstancePtr</em>, is empty.  <a href="group__llfifo__v5__0.html#gaba876eb888126638848fb2f89a9b4436">More...</a><br /></td></tr>
<tr class="separator:gaba876eb888126638848fb2f89a9b4436"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga12da547aa1c9a85e2b0b151f438ff9d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga12da547aa1c9a85e2b0b151f438ff9d5">XLlFifo_RxOccupancy</a>(InstancePtr)&#160;&#160;&#160;XStrm_RxOccupancy(&amp;((InstancePtr)-&gt;RxStreamer))</td></tr>
<tr class="memdesc:ga12da547aa1c9a85e2b0b151f438ff9d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_RxOccupancy returns the number of 32-bit words available (occupancy) to be read from the receive channel of the FIFO, specified by <em>InstancePtr</em>.  <a href="group__llfifo__v5__0.html#ga12da547aa1c9a85e2b0b151f438ff9d5">More...</a><br /></td></tr>
<tr class="separator:ga12da547aa1c9a85e2b0b151f438ff9d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga53af32ae6901462cc8d6fb9adc04655e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga53af32ae6901462cc8d6fb9adc04655e">XLlFifo_RxGetLen</a>(InstancePtr)&#160;&#160;&#160;XStrm_RxGetLen(&amp;((InstancePtr)-&gt;RxStreamer))</td></tr>
<tr class="memdesc:ga53af32ae6901462cc8d6fb9adc04655e"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_RxGetLen notifies the hardware that the program is ready to receive the next frame from the receive channel of the FIFO, specified by <em>InstancePtr</em>.  <a href="group__llfifo__v5__0.html#ga53af32ae6901462cc8d6fb9adc04655e">More...</a><br /></td></tr>
<tr class="separator:ga53af32ae6901462cc8d6fb9adc04655e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaadc3685592b060c0d864850e86be5c03"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#gaadc3685592b060c0d864850e86be5c03">XLlFifo_Read</a>(InstancePtr,  BufPtr,  Bytes)&#160;&#160;&#160;XStrm_Read(&amp;((InstancePtr)-&gt;RxStreamer), (BufPtr), (Bytes))</td></tr>
<tr class="memdesc:gaadc3685592b060c0d864850e86be5c03"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_Read reads <em>Bytes</em> bytes from the receive channel of the FIFO referenced by <em>InstancePtr</em> to the block of memory, referenced by <em>BufPtr</em>.  <a href="group__llfifo__v5__0.html#gaadc3685592b060c0d864850e86be5c03">More...</a><br /></td></tr>
<tr class="separator:gaadc3685592b060c0d864850e86be5c03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga922419fdcd342fa709fb07ec1a9e5577"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga922419fdcd342fa709fb07ec1a9e5577">XLlFifo_TxReset</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga922419fdcd342fa709fb07ec1a9e5577"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_TxReset resets the transmit channel of the FIFO specified by <em>InstancePtr</em>.  <a href="group__llfifo__v5__0.html#ga922419fdcd342fa709fb07ec1a9e5577">More...</a><br /></td></tr>
<tr class="separator:ga922419fdcd342fa709fb07ec1a9e5577"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga869bc4c1072da021e747a0a179bfe2da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga869bc4c1072da021e747a0a179bfe2da">XLlFifo_IsTxDone</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga869bc4c1072da021e747a0a179bfe2da"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_IsTxDone returns true if the transmission in the transmit channel of the FIFO, specified by <em>InstancePtr</em>, is complete.  <a href="group__llfifo__v5__0.html#ga869bc4c1072da021e747a0a179bfe2da">More...</a><br /></td></tr>
<tr class="separator:ga869bc4c1072da021e747a0a179bfe2da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga556524c17aee71ae8407540a5e2cd65f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga556524c17aee71ae8407540a5e2cd65f">XLlFifo_IsRxDone</a>(InstancePtr)</td></tr>
<tr class="memdesc:ga556524c17aee71ae8407540a5e2cd65f"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_IsRxDone returns true if the reception in the receive channel of the FIFO, specified by <em>InstancePtr</em>, is complete.  <a href="group__llfifo__v5__0.html#ga556524c17aee71ae8407540a5e2cd65f">More...</a><br /></td></tr>
<tr class="separator:ga556524c17aee71ae8407540a5e2cd65f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf2884c49ae41dc5c5317c2ef6df45a28"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#gaf2884c49ae41dc5c5317c2ef6df45a28">XLlFifo_TxVacancy</a>(InstancePtr)&#160;&#160;&#160;XStrm_TxVacancy(&amp;((InstancePtr)-&gt;TxStreamer))</td></tr>
<tr class="memdesc:gaf2884c49ae41dc5c5317c2ef6df45a28"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_TxVacancy returns the number of unused 32 bit words available (vacancy) in the send channel of the FIFO specified by <em>InstancePtr</em>.  <a href="group__llfifo__v5__0.html#gaf2884c49ae41dc5c5317c2ef6df45a28">More...</a><br /></td></tr>
<tr class="separator:gaf2884c49ae41dc5c5317c2ef6df45a28"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacd09ed5189e0b85994901102655964f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#gacd09ed5189e0b85994901102655964f7">XLlFifo_TxSetLen</a>(InstancePtr,  Bytes)&#160;&#160;&#160;XStrm_TxSetLen(&amp;((InstancePtr)-&gt;TxStreamer), (Bytes))</td></tr>
<tr class="memdesc:gacd09ed5189e0b85994901102655964f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_TxSetLen begins a hardware transfer of <em>Bytes</em> bytes out of the transmit channel of the FIFO specified by <em>InstancePtr</em>.  <a href="group__llfifo__v5__0.html#gacd09ed5189e0b85994901102655964f7">More...</a><br /></td></tr>
<tr class="separator:gacd09ed5189e0b85994901102655964f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1fa93f486abaaf35c7d599a8cd91b295"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga1fa93f486abaaf35c7d599a8cd91b295">XLlFifo_Write</a>(InstancePtr,  BufPtr,  Bytes)&#160;&#160;&#160;XStrm_Write(&amp;((InstancePtr)-&gt;TxStreamer), (BufPtr), (Bytes))</td></tr>
<tr class="memdesc:ga1fa93f486abaaf35c7d599a8cd91b295"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_Write writes <em>Bytes</em> bytes of the block of memory, referenced by <em>BufPtr</em>, to the transmit channel of the FIFO referenced by <em>InstancePtr</em>.  <a href="group__llfifo__v5__0.html#ga1fa93f486abaaf35c7d599a8cd91b295">More...</a><br /></td></tr>
<tr class="separator:ga1fa93f486abaaf35c7d599a8cd91b295"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga105828f79f13c07d571db218c5837fae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga105828f79f13c07d571db218c5837fae">XLlFifo_WriteTdr</a>(InstancePtr,  Tdest)</td></tr>
<tr class="memdesc:ga105828f79f13c07d571db218c5837fae"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_WriteTdr writes to the Transmit Destination Register (TDR)  <a href="group__llfifo__v5__0.html#ga105828f79f13c07d571db218c5837fae">More...</a><br /></td></tr>
<tr class="separator:ga105828f79f13c07d571db218c5837fae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga59307ef23e5b4b71d0d01cef8e06e247"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga59307ef23e5b4b71d0d01cef8e06e247">XLlFifo_ReadRdr</a>(InstancePtr)&#160;&#160;&#160;<a class="el" href="group__llfifo__v5__0.html#ga7526eab563fa4e0fe8b60474e96afe55">XLlFifo_ReadReg</a>((InstancePtr)-&gt;BaseAddress, <a class="el" href="group__llfifo__v5__0.html#gaf0240fc89cce2e27e1943d2e23a5af25">XLLF_RDR_OFFSET</a>)</td></tr>
<tr class="memdesc:ga59307ef23e5b4b71d0d01cef8e06e247"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_ReadTdr returns the contents of the Receive Destination Register(RDR).  <a href="group__llfifo__v5__0.html#ga59307ef23e5b4b71d0d01cef8e06e247">More...</a><br /></td></tr>
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Typedefs</h2></td></tr>
<tr class="memitem:ga89057d90d6eacdbe8adc766f53f60ed7"><td class="memItemLeft" align="right" valign="top">typedef struct <a class="el" href="struct_x_ll_fifo.html">XLlFifo</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga89057d90d6eacdbe8adc766f53f60ed7">XLlFifo</a></td></tr>
<tr class="memdesc:ga89057d90d6eacdbe8adc766f53f60ed7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef defines a run-time instance of an <a class="el" href="struct_x_ll_fifo.html" title="This typedef defines a run-time instance of an XLlFifo device. ">XLlFifo</a> device.  <a href="group__llfifo__v5__0.html#ga89057d90d6eacdbe8adc766f53f60ed7">More...</a><br /></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga874c22807476dc0ffec670c38f452443"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga874c22807476dc0ffec670c38f452443">XLlFifo_CfgInitialize</a> (<a class="el" href="struct_x_ll_fifo.html">XLlFifo</a> *InstancePtr, XLlFifo_Config *Config, UINTPTR EffectiveAddress)</td></tr>
<tr class="memdesc:ga874c22807476dc0ffec670c38f452443"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_CfgInitialize initializes an XPS_ll_Fifo device along with the <em>InstancePtr</em> that references it.  <a href="group__llfifo__v5__0.html#ga874c22807476dc0ffec670c38f452443">More...</a><br /></td></tr>
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<tr class="memitem:ga3debde0a34325b3f314d15fe6f43a7ee"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga3debde0a34325b3f314d15fe6f43a7ee">XLlFifo_Initialize</a> (<a class="el" href="struct_x_ll_fifo.html">XLlFifo</a> *InstancePtr, UINTPTR BaseAddress)</td></tr>
<tr class="memdesc:ga3debde0a34325b3f314d15fe6f43a7ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">XLlFifo_Initialize initializes an XPS_ll_Fifo device along with the <em>InstancePtr</em> that references it.  <a href="group__llfifo__v5__0.html#ga3debde0a34325b3f314d15fe6f43a7ee">More...</a><br /></td></tr>
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<tr class="memitem:ga549da0fb83b3bb11ea6401b8001f9c4e"><td class="memItemLeft" align="right" valign="top">XLlFifo_Config *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__llfifo__v5__0.html#ga549da0fb83b3bb11ea6401b8001f9c4e">XLlFfio_LookupConfig</a> (u32 DeviceId)</td></tr>
<tr class="memdesc:ga549da0fb83b3bb11ea6401b8001f9c4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Look up the hardware configuration for a device instance.  <a href="group__llfifo__v5__0.html#ga549da0fb83b3bb11ea6401b8001f9c4e">More...</a><br /></td></tr>
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